1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device having a circuit for compen sating for variations in a discriminating voltage of a memory cell caused by a parasitic capacitance of a gate transistor of the memory cell upon activation thereof.
2. Description of the Related Art
In a so-called dynamic semiconductor memory device having memory cells consisting of a capacitor and a gate transistor, the memory capacitor of each memory cell is connected to a bit line through the gate transistor, and a charging stage of the capacitor is detected by a sense amplifier connected to the bit line to discriminate logic "0" or "1" of the memory cell. The ON/OFF operation of the gate transistor is performed via a word line. In this case, the word line may be capacitively coupled to the memory capacitor because of the parasitic capacitance of the gate transistor. If a word line voltage rises to enable the memory cell, the memory cell voltage is influenced by noise through the aforementioned parasitic capacitance and undesirably varies. As a result, the memory cell discriminating voltage i.e., threshold voltage for discriminating the logic "0" or "1" of the memory cell content, is deviated from an accurate intermediate value between logic "0" and logic "1" voltages. The margin for noise is reduced and a read error of the memory cell tends to occur.
In order to solve this problem, in a conventional dynamic semiconductor memory device, a dummy transistor is formed in each memory cell to cancel the parasitic capacitance of the gate transistor by its own parasitic capacitance, hereby variations in discriminating voltage are prevented. However, if the dummy transistors are arranged in units of memory cells, the total number of dummy transistors is increased, and a large area is occupied by the dummy transistors in the memory device as a whole. As a result, the memory capacity of the semiconductor memory device per unit area is reduced.